Digital/ASIC Design

ADCGDS2RTL Design & Verification

  • Architecture
  • System-on-Chip Building Blocks
  • Interfaces
  • Test Chip Assembly
  • System Verilog
  • Questa™ Vanguard Partner

ASIC Processing

  • Synthesis
  • Design For Test
  • Static Timing Analysis
  • Formal Equivalence
  • Back Annotated Delay Simulations

Physical Design

  • Full Physical Design Flow Expertise from RTL to GDSII down to 32nm
  • Automated and Full Custom Options
  • Route Fixing with Noise Analysis
  • Clock Tree Management, Clock Gating, Balancing, Skew Reduction and Short Insertion Delays
  • Full Chip Floor Planning
  • Timing Closure with Noise Fixing