Digital Verification Capabilities
ASIC, FPGA, IP, SoC
- UVM / System Verilog Expertise
- Test bench planning from design requirements
- Regression analysis and coverage collection
- Continuous improvement with new tool integration
- Verification IP integration
- Constrained random and directed testing
- Assertion Based verification
- Test bench component development for reuse
- HDL agnostic – support both Verilog and VHDL
AsicNorth provides full lifecycle support for verifying your design. This starts with requirement generation to balance performance, schedule, and cost while also ensuring there is clear pass/fail criteria for verification. Testbench development continues with documented development and finishes with coverage closure and RTL sign-off.
Verification support continues through the physical design process including gate-level simulation with annotated delays (SDF files) to support the timing signoff process.
Tools
Cadence: Xcelium, Verisium, Avery VIP
Siemens: Questa, QVIP
External debug: CoreSight
Version and Requirement Management: Git, Subversion, Jira
